1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to one or more low dielectric constant insulation layers formed on an integrated circuit structure and a method of making same.
2. Description of the Related Art
In the formation of integrated circuit structures, patterned conductive layers must be used to provide electrical interconnection between active and passive devices comprising the integrated circuit structure.
However, the shrinkage of feature sizes in such integrated circuit structures includes shrinkage of the horizontal spacing between adjacent conductors on the same plane. However, such shrinkage of feature size results in a corresponding rise in the impedance of the conductors, as well as crosstalk between the conductors. Such increases in impedance in the integrated circuit structure can result in degradation of the performance of the integrated circuit structure, e.g., reduce the response time of the active devices by increasing the impedance of the lines.
It would, therefore, be desirable if one could reduce the amount of capacitance formed between adjacent lines, either horizontally or vertically, to thereby reduce the impedance of the lines.
Theoretically, this could be done by substituting a different insulation material having a lower dielectric constant, e.g., using some insulation material other than the commonly used SiO.sub.2, or by somehow reducing the dielectric constant of the particular insulation material being used, e.g., somehow reducing the dielectric constant of a SiO.sub.2 insulation layer.
Of these two alternatives, it has been demonstrated to be preferable to achieve such a lowering of capacitance without the substitution of new insulation materials into the integrated circuit structure.